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LASO - Learn ARM with Source Open

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锁相环和分频器

锁相环 PLL

PLL: Fin -> Fout 倍频		XPLL_CON
MUX: 0/1 选择器 SRC选择源	CLK_SRC
DIV: /2-16 分频器 DIV		CLK_DIV

REGISTER DESCRIPTION
OM[0]: cpu pin OM[0]=0, XXTI=24M
Fin_PLL: 24Mhz
APLL: APLL_CON: e0100100: 0xa07d0301 => 1000Mhz

分频器 Divider

Mux_APLL: CLK_SRC0, 0xe0100200: 10001111 [0]=> 1
Mux_MSYS: CLK_SRC0, 0xe0100200: 10001111 [16]=> 0
DIV_APLL: CLK_DIV0, 0xE0100300: 14131440 [2:0]=> 0 = /1
DIV_APLL: CLK_DIV0, 0xE0100300: 14131440 [10:8]=> 100 = /5

寄存器配置

[FriendlyLEG-TINY210]# md 0xe0100100
e0100100: a07d0301 00000000 a29b0c01 00000000    ..}.............
e0100110: a8500303 00000000 00000000 00000000    ..P.............
e0100120: a06c0603 00000000 00000000 00000000    ..l.............
e0100130: 00000000 00000000 00000000 00000000    ................
e0100140: 00000000 00000000 00000000 00000000    ................
e0100150: 00000000 00000000 00000000 00000000    ................
e0100160: 00000000 00000000 00000000 00000000    ................
e0100170: 00000000 00000000 00000000 00000000    ................
e0100180: 00000000 00000000 00000000 00000000    ................
e0100190: 00000000 00000000 00000000 00000000    ................
e01001a0: 00000000 00000000 00000000 00000000    ................
e01001b0: 00000000 00000000 00000000 00000000    ................
e01001c0: 00000000 00000000 00000000 00000000    ................
e01001d0: 00000000 00000000 00000000 00000000    ................
e01001e0: 00000000 00000000 00000000 00000000    ................
e01001f0: 00000000 00000000 00000000 00000000    ................

[FriendlyLEG-TINY210]# md 0xe0100200
e0100200: 10001111 00000000 00000000 00000000    ................
e0100210: 66667777 00000000 00000000 00000000    wwff............
e0100220: 00000000 00000000 00000000 00000000    ................
e0100230: 00000000 00000000 00000000 00000000    ................
e0100240: 00000000 00000000 00000000 00000000    ................
e0100250: 00000000 00000000 00000000 00000000    ................
e0100260: 00000000 00000000 00000000 00000000    ................
e0100270: 00000000 00000000 00000000 00000000    ................
e0100280: ffffffff ffffffff 00000000 00000000    ................
e0100290: 00000000 00000000 00000000 00000000    ................
e01002a0: 00000000 00000000 00000000 00000000    ................
e01002b0: 00000000 00000000 00000000 00000000    ................
e01002c0: 00000000 00000000 00000000 00000000    ................
e01002d0: 00000000 00000000 00000000 00000000    ................
e01002e0: 00000000 00000000 00000000 00000000    ................
e01002f0: 00000000 00000000 00000000 00000000    ................

[FriendlyLEG-TINY210]# md 0xe0100300
e0100300: 14131440 00000400 00000000 00000000    @...............
e0100310: 99990000 00000000 00070000 00000000    ................
e0100320: 00000000 00000000 00000000 00000000    ................
e0100330: 00000000 00000000 00000000 00000000    ................
e0100340: 00000000 00000000 00000000 00000000    ................
e0100350: 00000000 00000000 00000000 00000000    ................
e0100360: 00000000 00000000 00000000 00000000    ................
e0100370: 00000000 00000000 00000000 00000000    ................
e0100380: 00000000 00000000 00000000 00000000    ................
e0100390: 00000000 00000000 00000000 00000000    ................
e01003a0: 00000000 00000000 00000000 00000000    ................
e01003b0: 00000000 00000000 00000000 00000000    ................
e01003c0: 00000000 00000000 00000000 00000000    ................
e01003d0: 00000000 00000000 00000000 00000000    ................
e01003e0: 00000000 00000000 00000000 00000000    ................
e01003f0: 00000000 00000000 00000000 00000000    ................

分析 ARMCLK 的产生

Q1: OM[0] = 0, SRC->XXTI (24Mhz)	由硬件连线决定
Q2: APLLCON (24M->1000M)	0xE0100100 => 0xa07d0301
	Fout = Fin * MDIV / (PDIV * 2 ^ SDIV-1)
			= 24M * 0x7d / (3 * 2^0)
			= 24M * 125 / (3*1) = 1000M
Q3: CLK_SRC0	0xE0100200 => 0x10001111
	bit[0]=1 	MUXPLL = 1, Fout_APLL
Q4: CLK_SRC0	0xE0100200 => 0x10001111
	bit[16]=0 	Fout_APLL = 1G
Q5: CLK_DIV0	Address = 0xE0100300 => 0x14131440
	APLL_RATIO  [2:0] 	n=0+1	
	ARMCLK = Fout_APLL/n = 1G/1 = 1Ghz

举例: UART 串口时钟 PCLK_PSYS 的生成过程

Mux_PSYS: CLK_SRC0, 0xe0100200: 10001111 [24]=>0  Fout_mpll

MPLL: MPLL_CON: 0xa29b0c01 => 667Mhz (p358)
	Equation to calculate the output frequency:
	FOUT = MDIV X FIN / (PDIV X 2^SDIV)
	Fout = (0x29b)*24M/(12 * 2^1) = 667Mhz
Mux_MPLL: CLK_SRC0, 0xe0100200: 10001111 [4]=> 1  Fout_mpll

DIV_HCLKP: CLK_DIV0, 0xE0100300: 14131440 [27:24]=> 0100 = /5 -> 667/5 = 133Mhz
DIV_PCLKP: CLK_DIV0, 0xE0100300: 14131440 [30:28]=> 001 = /2 -> 133/2 = 66Mhz

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