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LCD 寄存器配置

LCD 寄存器分类

SFR 特殊功能寄存器 (部分)
控制类
	DISPLAY_CONTROL
	VIDCON0 
	VIDCON1
	SHADOWCON
	
时序参数
	VIDTCON0
	VIDTCON1
	VIDTCON2
	
数据类	
	VIDW00ADD0B0
	VIDW00ADD1B0
	
窗口参数
	WINCON0
	VIDOSD0A
	VIDOSD0BB

初始化配置

	// GPIO Functional as LCD Signals
	GPF0CON = 0x22222222;		// GPF0[7:0]
	GPF1CON = 0x22222222;		// GPF1[7:0]
	GPF2CON = 0x22222222;		// GPF2[7:0]
	GPF3CON = 0x22222222;		// GPF3[7:0]

	// XpwmTOUT1 GPD0_1 output high level
	// GPD0 Control Register (GPD0CON, R/W, Address = 0xE020_00A0)
	GPD0CON |= 1<<4;
	GPD0DAT |= 1<<1;

	// clock init (CLK_SRC1, CLK_DIV1 are optional)
	DISPLAY_CONTROL = 2<<0;		// 10: RGB=FIMD I80=FIMD ITU=FIMD

	// LCD SFR init
	// ENVID [1] Video output and the logic immediately enable/disable. 
	//	0 = Disable the video output and the Display control signal. 
	//	1 = Enable the video output and the Display control signal. 
	// ENVID_F [0] Video output and the logic enable/disable at current frame end. 
	//	0 = Disable the video output and the Display control signal. 
	//	1 = Enable the video output and the Display control signal.  
	// see 210.pdf p1228
	VIDCON0 |= 1<<0 | 1<<1 ;

	// CLKVAL_F [13:6] Determine the rates of VCLK and CLKVAL[7:0]  
	// VCLK = Video Clock Source / (CLKVAL+1)  where CLKVAL >= 1  
	VIDCON0 |= 1<<4;

	// LCD module para, see H43-HSD043I9W1.pdf p13
	VIDCON0 |= 14<<6;	// 166M/(14+1) = 11M < 12M(max)

	// LCD module para, see H43-HSD043I9W1.pdf p13
	// IHSYNC  [6]  Specifies the HSYNC pulse polarity. 
	//	0 = Normal               
	//	1 = Inverted 
	// IVSYNC  [5]  Specifies the VSYNC pulse polarity. 
	//	0 = Normal               
	//	1 = Inverted 	
	VIDCON1 |= 1<<5 | 1<<6;

	// LINEVAL [21:11] 
	// HOZVAL [10:0] 
	VIDTCON2 = (ROW - 1)<<11 | (COL - 1)<<0;	// 479*271

	// ENWIN_F [0] Video output and the logic immediately enable/disable. 
	//	0 = Disable the video output and the VIDEO control signal. 
	//	1 = Enable the video output and the VIDEO control signal. 
	WINCON0 |= 1<<0;

	// BPPMODE_F [5:2] Select the BPP (Bits Per Pixel) mode Window image.  
	// 1011 = unpacked 24 BPP (non-palletized R:8-G:8-B:8 )  
	WINCON0 |= 0xB<<2;

	// WSWP_F  [15]  Specifies the Word swap control bit. 
	// 0 = Swap Disable         
	// 1 = Swap Enable 
	WINCON0 |= 1<<15;	

	// left top pixel (0, 0)
	VIDOSD0A |= 0<<11;
	VIDOSD0A |= 0<<0;

	// right bottom pixel (479, 271)
	VIDOSD0B |= (COL - 1)<<11;
	VIDOSD0B |= (ROW - 1)<<0;

	// fb address
	VIDW00ADD0B0 = FB_ADDR;
	VIDW00ADD1B0 = FB_ADDR + ROW * COL * 4;

	// LCD module para, see H43-HSD043I9W1.pdf p13
#define HSPW 	(40 - 1)
#define HBPD 	(5 - 1)
#define	HFPD 	(2 - 1)
#define VSPW	(8 - 1)
#define VBPD 	(8 - 1)
#define VFPD 	(2 - 1)
	VIDTCON0 = VBPD<<16 | VFPD<<8 | VSPW<<0;
	VIDTCON1 = HBPD<<16 | HFPD<<8 | HSPW<<0;

	// C0_EN_F  0  Enables Channel 0. 
	//	0 = Disables          1 = Enables 
	SHADOWCON = 0x1;	

编程实现

===========
新建项目:start.s  main.c 
armasm start.s 汇编器
armcc main.c 编译器

fromelf 工具-查看反汇编
fromelf 工具-生成bin文件

axf 可执行文件 -> bin 可以用 vivi 下载的格式

> load ram 0x31000000 0 x

需要修改的地方:
1. 设置好sp,栈指针 (C程序函数会用到栈来存放局部变量)
2. 测试uart 的输出功能 (无限循环输出 'a')
3.  load ram 0x31000000 0 x


编写测试程序:
1. 定义 FB_ADDR	0x32000000

2. 定义
 ROW=480	COL=640

3. for (i, j) 两重循环对 FB 进行颜色赋值

4. 定义 RGB16(r,g,b) 	生成 16bit 的颜色


LCD 控制器的初始化操作:
1. 设置 FB_ADDR = 0x32000000
2. 设置 Enable LCD Controller 
3. 设置了 LCD Signals = 0b10 第3种功能
4. 设置 MODE: TFT Panel, BPPMODE=16bit
-----------------------------------------
Timing时间参数:
刷新频率:1 second 需要传送多少帧 = 60hz
场同步周期:1/60 = 16.67ms 传送1个帧 (场)

Tv = (16.68ms) = Tvspw (0.06ms) + Tvbpd (1.02ms) + Td(15.25ms) + Tvfpd (0.35ms)

Td = 480 * Th => Th = 15.25ms / 480 = 31.77 us

Th = 31.77us = Thspw (3.77us) + Thbpd (1.89us) + Tline (25.17us) + Thfpd (0.94us)

Tline = 640 * Tp => Tp = 25.17us/640 =  0.04 us => 25Mhz



Thspw (3.77us) + Thbpd (1.89us) + Tline (25.17us) + Thfpd (0.94us)
0.04 us = VCLK
94VCLK + 47VCLK + 640VLCK + 24VCLK = 805VCLK (640 column)
HSPW	94
HBPD	47
LINEVAL	640
HFPD	24

Tvspw (0.06ms) + Tvbpd (1.02ms) + Td(15.25ms) + Tvfpd (0.35ms)
31.77 us = HCLK
2HCLK + 32HCLK + 480HCLK + 11HCLK = 525HCLK (480 row)
VSPW	2
VBPD	32
HOZVAL	480
VFPD	11


参考链接:
http://www.docin.com/p-318463264.html

akaedu.gensee.com

http://akaedu.gensee.com/webcast


分形图像  特点 - 自相似

Julia 集合


F(z) = Z*Z - 0.75

Z = x + yi

Z * Z = (x+yi)(x+yi) = (x*x - y*y) + (2*x*y)i

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